This invention relates to a method of operating a charge-coupled device.
FIG. 1 of the accompanying drawings illustrates schematically a four-phase CCD fabricated on a p-type silicon die 2 having an n-type buried channel 4. A layer of dielectric material (not shown) overlies the upper surface of the die, and conductive gates 8 are formed over the dielectric layer. The device may be fabricated by use of known MOS technology. Thus, the dielectric layer is made of silicon dioxide and the gates 8 are made of polysilicon and are deposited in two stages over the dielectric layer so that each two adjacent gates comprise a lower level polysilicon gate and an upper level polysilicon gate that partially overlaps the adjacent lower level gate(s). This method of fabricating a CCD, applied to a two-phase device, is described in Kim, "Two-Phase Coupled Linear Imaging Devices With Self-Aligned Implanted Barrier," International Electron Device Meeting, 1974.
A transfer clock driver 10 generates a four-phase clock signal. The clock signal has a rectangular voltage waveform, with the four clock phases being offset in phase relative to each other by 90.degree. as shown in FIG. 2. Each gate is connected to one of the four clock phases, so that a gate 8.sub.1 connected to clock phase 1 is positioned between a gate 8.sub.4 connected to clock phase 4 and a gate 8.sub.2 connected to clock phase 2, and a gate 8.sub.3 connected to clock phase 3 is positioned between a gate 8.sub.2 connected to clock phase 2 and a gate 8.sub.4 connected to clock phase 4. Thus, four sets of gates are defined, connected to the first, second, third and fourth clock phases respectively, and four sets of storage cells 12 are formed in the channel 4 beneath the four sets of gates respectively. The cells may also be considered to be in groups each containing a cell 12.sub.1 and the three succeeding cells 12.sub.2, 12.sub.3 and 12.sub.4.
The waveforms in FIG. 1 represent the channel potential at the times indicated in FIG. 2 as t.sub.1, t.sub.2, t.sub.3 and t.sub.4. At the time t.sub.1, clock phases 1 and 4 are both high and clock phases 2 and 3 are both low, and accordingly, for each group of four gates the voltages applied to the gates establish a potential well in the cell 12.sub.4 of one group and the cell 12.sub.1 of the next group, between potential barriers established in the cells 12.sub.3 and 12.sub.2 that immediately precede and succeed the cells 12.sub.4 and 12.sub.1 respectively. A charge packet of electrons is trapped in the potential well.
At time t.sub.2, the voltage of phase 4 has fallen and therefore the channel potential in the cell 12.sub.4 has increased to the same level as the channel potential in the cell 12.sub.3. The channel potential in the cell 12.sub.2 has decreased to the level of the channel potential in the cell 12.sub.1. When the channel potential in the cell 12.sub.4 increases, charge present in the cell 12.sub.4 of a group of cells will be transferred forwards into the potential well defined by the cells 12.sub.1 and 12.sub.2 of the next group. However, if the clock edge is very fast, such as would occur of the CCD is used as the acquisition stage of a high speed analog-to-digital converter, a significant proportion of the charge will spill back into the potential well defined by the cells 12.sub.1 and 12.sub.2 of the group that includes the cell 12.sub.4. A similar spill back occurs when phase 1 falls to its low level, as indicated at time t.sub.3.
FIG. 3 is an enlarged view of the voltage waveform applied to the gates. FIG. 3 shows that the voltage level does not change instantaneously, but over an interval from the time t.sub.5 to the time t.sub.6. This interval may be about one-tenth of the clock period. Under low charge level conditions, the interval from t.sub.5 to t.sub.6 is the time available for charge to transfer from one cell (the transferring cell) to the next succeeding cell (the receiving cell) with no possibility of spill back. At the time t.sub.6, when the clock voltage reaches its minimum level, the channel potential of the transferring cell reaches its maximum level, which is the same as the channel potential of the preceding cell, and spill back can occur. Under high charge level conditions, such that the Fermi level in the transferring cell is raised, spill back can occur before the time t.sub.6.
It is known to employ a four-phase charge-coupled device (CCD) in a serial-parallel-serial (SPS) analog shift register for high speed signal acquisition. See, for example, U.S. Pat. No. 4,725,748, issued Feb. 16, 1988 (Hayes et al).
An SPS analog shift register comprise an input serial register, an output serial register, and a parallel register that connects the input serial register to the output serial register. The parallel register is composed of multiple segments, each comprising a serial register, extending between the input register and the output register. An input signal is sampled at an input diode of the input register and consecutive samples are shifted through the input register. When the input register is full, the samples are shifted into respective segments of the parallel register, emptying the input register. The input register is filled and emptied again, and as each group of samples is shifted into the parallel register the samples that were previously shifted into the parallel register are advanced by one step through the parallel register. Ultimately, each group of samples reaches the output register, and is shifted serially through the output register to an output node of the SPS shift register.
Part of a practical implementation of the SPS register described in U.S. Pat. No. 4,725,748 is illustrated diagramatically in FIG. 4. FIG. 4 shows a portion of the input serial register 20 at its junctures with two of the segments 22, 24 of the parallel register. In FIG. 4, the lower level gates are marked in solid lines, the upper level gates in dashed lines, and the buried channel in dot-dashed lines. The efficiency with which charge is transferred along a CCD shift register depends on the length of the cells that are defined in the channel beneath the gates respectively: the shorter the cells, the greater the efficiency. The length of the longest cell limits the efficiency of the CCD. The length of a cell is the maximum distance that must be traveled by signal charge in order to leave the cell. It is clear from inspection of FIG. 4 that the maximum distance D that signal charge must travel in the serial direction in order to pass from an odd cell to an even cell is greater than the maximum distance d that the signal charge needs to travel in the serial direction in order to pass from an even cell to an odd cell. This is particularly so in the case of the cell 12.sub.1, where charge may enter the region at the upper end of the segment 22 of the parallel register because of the need to provide a space between the first gate of the parallel register, which is a lower level gate, and the lower level gates of the serial input register.
The problem of charge spill back is less serious with cells that are short (in the direction of charge transfer) than with cells that are long. This is because more charge is transferred from a transferring cell to its receiving cell before the clock voltage applied to the gate over the transferring cell reaches its final low level in the case of a short transferring cell than in the case of a long transferring cell.
Spill back may affect the charge transfer efficiency of a CCD. The charge transfer efficiency (CTE) of a charge coupled device is the ratio of charge transferred to a storage cell from its neighboring cell during a clock phase to the initial charge in the neighboring cell at the beginning of the clock phase. A high CTE is desirable, to prevent substantial degradation of the signal passing through the device.
FIG. 5 represents the electrical characteristics of a four phase CCD of known type. In FIG. 5, curve A represents variation in CTE (right ordinate) as a function of common mode voltage (bias charge) while curve B represents the differential CCD output (left ordinate) in response to a two-volt input pulse as a function of common mode voltage. It will be noted that the curve B is composed of two substantially linear segments joined by a curved portion. It is desirable to operate the CCD within a range of common mode voltages for which the curve B is linear. Typically the common mode voltage varies by about two volts during operation of a CCD. In the case of FIG. 5, this indicates that the common mode voltage cannot be higher than about 9 volts, which implies that the CTE is about 0.995.
In an implementation of the SPS register that is illustrated diagrammatically in FIG. 4, the difference in cell length between the longer cells and the shorter cells is about 45%, but the area of the shorter, rectangular cells is about the same as the area of the longer, delta-shaped cells and therefore the Fermi level in the shorter cells is not affected significantly by the charge level. If the cells were all rectangular and of the same width, and the longer cells were more than about 20% longer than the shorter cells, the area of the shorter cells would be significantly less than the area of the longer cells. If such a CCD were operated at a high charge level, spill back might be exacerbated by the increase in Fermi level in the shorter cells. FIG. 6 illustrates a three-phase CCD in which the cells 14.sub.1 are substantially longer than the cells 14.sub.2 and 14.sub.3. When phase 1 is low and phases 2 and 3 are high, charge is stored in the cells 14.sub.2 and 14.sub.3 (waveform A). If the FIG. 6 CCD is operated at a high charge level, the quantity of charge stored in the cell 14.sub.2 increases the Fermi level in the cell and results in the channel potential in the cell 14.sub.2 being substantially higher, indicated by a dashed line, than it would be at a lower charge level (solid line). Therefore, when phase 2 starts to go low, the channel potential in the cell 14.sub.2 reaches the same level as in the cell 14.sub.1 before the phase 2 clock potential reaches its low level, and spill back can occur. Waveforms C and D indicate the channel potential profile when phase 2 reaches its low level and when phase 1 has risen to its high level, respectively.